1. Field of the Invention
This application generally relates to semiconductor memories and more specifically to sense amplification suitable for DRAM circuitry which may employ a hierarchical structure.
2. Description of the Related Art
Generally, DRAM is built as a separate integrated circuit chip from any digital logic, thus allowing for use of a specialized DRAM process and structures such as trench or other 3D capacitors. Such structures may be used to create high capacitance structures in small areas, thus leading to high DRAM cell density on the DRAM chips. However, these structures are not compatible with logic processes, and the large capacitances may lead to high power consumption and high temperatures.
For memory on integrated circuit chips created through use of a logic process, SRAM memory has typically been used. However, SRAM memory is often much less dense than DRAM memory. As a result, SRAM requires more space on a chip than DRAM does. Also, SRAM may require more power and generate a higher temperature than DRAM.
Additionally, traditional DRAM designs have used a sense amplifier to sense whether the value stored in a DRAM cell is high or low. These sense amplifiers typically operate through a charge sharing mechanism, thus requiring that the capacitance of the DRAM cell be matched (close to a desired ratio) with other components of the DRAM device.
The sense amplifiers are traditionally configured as positive feedback latches similar to an SRAM cell which can be selectively coupled to a pair of complementary bit-lines (bit-line and bit-line bar). During the bitline pre-charge period, the two differential bitlines are set to the same voltage. After the wordline is activated or turns on, DRAM cells associated with the wordline start charge sharing between the DRAM cell capacitor and the associated bit-line. Depending on the charge stored in the DRAM cell capacitor, the bitline or bitline bar will change voltage (move) accordingly and settle down to a new voltage value, which is an equilibrium value between the value on the capacitor and the pre-charged value of the bitline. Meanwhile, the complementary bitline will remain at the pre-charged value (voltage level).
After the charge sharing occurs and reaches an equilibrium, the sense amplifier is coupled to the two bit-lines. This coupling causes the sense amplifier to drive the two bitlines in opposite directions, one toward ground and the other toward a positive power supply voltage. In driving the two bitlines, the sense amplifier effectively amplifies the differential between the two bitlines, and this differential may be sensed in order to determine what value was stored in the DRAM cell which was used to cause charge sharing originally.
In a numerical example, if a Vcc of 5V is used, the pre-charge voltage of the two bitlines will be 2.5V. Once charge sharing occurs, one of the bitlines will be slightly lower or higher than 2.5V. For example, the bitline may be at 2.75V while the bitline bar is at 2.5V. When the two bitlines are coupled to the sense amplifier, the bitline is then driven to 5V and the bitline bar is driven to ground (0V) by the positive feedback action of the sense amplifier.
A method and apparatus for sense amplification is disclosed. In one embodiment, this is a method of amplifying signals in a DRAM including sharing charge between a cell and a first conductor of a first pair of complementary conductors; and driving a voltage of the first conductor of the first pair and a voltage of a second conductor of the first pair in the same direction relative to a power supply voltage.
In an alternate embodiment, this is an apparatus. The apparatus includes a first transistor having a first terminal, a second terminal and a gate. The apparatus also includes a second transistor having a first terminal, a second terminal and a gate, the gate of the second transistor coupled to the first terminal of the first transistor, the first terminal of the second transistor coupled to the gate of the first transistor. Moreover, the apparatus also includes a third transistor having a first terminal, a second terminal, and a gate, the first terminal of the third transistor coupled to the second terminal of the first transistor and the second terminal of the second transistor, the gate of the third transistor coupled to a power enable conductor, the second terminal of the third transistor coupled to a power supply node.
In another alternate embodiment, this is a DRAM cell array. The DRAM cell array includes a set of cells selectively coupled to a bitline conductor and a set of cells selectively coupled to a bitline bar conductor. The DRAM cell array also includes a half sense amplifier coupled to the bitline conductor and to the bitline bar conductor.
In yet another alternate embodiment, this is a method of amplifying. The method includes coupling a half sense amplifier to a bitline conductor and a bitline bar conductor. The method also includes amplifying a differential between the bitline conductor and the bitline bar conductor through operation of the half sense amplifier.
In still another alternate embodiment, this is an ASIC. The ASIC includes a digital logic circuit block and a DRAM circuit block, the DRAM circuit block including a set of cells coupled to a half sense amplifier.
Each of these embodiments may further include driving voltage of a first set of complementary conductors in the same direction relative to a ground potential and then driving voltage of a second set of complementary conductors in opposite directions relative to a ground potential when the second set of complementary conductors are coupled to the first set of complementary conductors or circuitry configured to achieve these results.